1. Field of the Invention
This invention relates generally to a data processing system, and more particularly to a microprogrammed control unit which is implemented with programmable logic arrays.
2. Prior Art
In a microprogrammed processor computer there are two levels of programming; namely, the microinstruction level and the macroinstruction level. The macroinstruction level is contained in a sequence or set of instructions known collectively as a program which is prepared by a programmer or operator of the computer to solve particular problems. The macroinstruction level program for the computer includes a set of machine operations, such as addition, multiplication, and the like, which can be selected at the programmer's disposal. Within the computer, these machine operations are capable of selecting a set of microroutines which include microinstructions corresponding to such operations as shifting, counting, word transfer and the like, which instructions are selectible by the machine designer.
A portion of each instruction in the macroinstruction level is a binary number called the operation code, and this code is supplied to a control unit within the machine to select one of a number of possible execution sequences. In a microprogram computer, the operation code of a machine instruction is employed as an address into a control store. The microprogram having an entry point at that address is executed to achieve the desired control function. Microinstructions stored in the control store cause the control unit within the machine to carry out the basic control functions of the processor and cause the arithmetic and logic unit (ALU) to carry out the basic data processing functions of the processor on data which is stored in a register unit.
The two basic functions of the microprogrammed control store in conjunction with the control unit are called the "fetch" function and the "execute" function. In performing the fetch function, the control section, which includes the control unit and control store, executes a series of microinstructions which cause a macroinstruction to be read (or fetched) from the external store containing such macroinstructions into an instruction register within the control unit.
For each macroinstruction which has been fetched or supplied into the instruction register, there is a particular series of microinstructions (microroutine) in the microprogram control store which must be executed to carry out the execute function corresponding to that macroinstruction. For example, if the macroinstruction included a "register add" instruction, the microroutine would access data from the appropriate registers in the register unit and cause the arithmetic and logic unit to add the selected data, and would then store the resultant total in an appropriate register within the register unit. After completing the execute function, the control section would then return to the fetch function mode to read or fetch another macroinstruction.
In order to access the correct microroutine in the control store, the operation code portion of the contents of the instruction register must be employed to specify the initial microinstruction address for the microroutine. This requirement may present a considerable problem in that the operation code portion of the various instructions for a particular processor is of varying of different length. In the case of simple processors, the length of some of the operation code portions or fields may exceed the number of bits which are permitted for addressing the control store containing the microinstructions. As one example, the instruction format for a 16 bit macroinstruction set may contain an operation code field which varies from four to 10 bits in length. In the event the control store has less than several hundred words of storage, the operation code may not be employed directly to specify the address of the appropriate microroutine, since the address would in certain instances exceed the storage bounds of the control store. In the event the control store contains more than 1024 words of storage, corresponding to 10 address bits, it is desirable to allow the microprogrammer the choice of starting addresses, rather than having such starting addresses specified directly by the operation code, in which event such addresses may occur at awkward places in the microprogram. Accordingly, it is desirable to have a unit which transforms or maps an arbitrary operation code into an arbitrary control store address. It has been the practice in the past to employ discrete logic gates to perform this function. However, in an effort to minimize the number of gates employed, the choice of operation codes and starting addresses has been limited.
Control stores have been implemented in the past with read-only memories (ROM). A read-only memory as a control store requires exhaustive coding of all of its address input lines. Accordingly, in a processor with macroinstructions having 10 bits of instruction as operation code information, the number of address lines must be at least equal to 10. Accordingly, a control store implemented with a read-only memory would require at least 1,024 locations.
The requirement for such a large read-only memory array can sometimes be obviated by employing a two-stage control memory, with one state performing partial decoding and the other performing the actual control. However, this technique is not general and because of the relatively slow access of two levels of MOS read-only memories, system throughput may be compromised to an unacceptible level. Furthermore, in a read-only memory implementation if several instructions share parts of common code segments in the microprogram, either those segments must be repeated or a microprogram jump to a common segment (or subroutine) must be provided. Because such jumps require the insertion in the microprogram of a specific microinstruction to perform that function, which instructions must be stored in the read-only memory and require an additional cycle to execute, they degrade the system throughput.
It has also been the practice in the past to employ the technique of multiplexing the required codes into the read-only memory elements when not all code combinations of instruction data and timing data are employed. This technique effectively compresses the data to reduce the number of read-only memory words necessary to store the output data. Although the use of multiplexers significantly reduces the number of read-only memory storage required, it adds to the delay time to achieve the proper output levels. Furthermore, this technique is relatively difficult to implement, is not easily changed, and is not general.